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| DS28CM00 IC/SMBus Silicon Serial Number www.maxim-ic.com GENERAL DESCRIPTION The DS28CM00 is a low-cost, electronic registration number to provide an absolutely unique identity that can be determined with the industry standard IC and SMBus interface. The registration number is a factory-lasered, 64-bit ROM that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit family code (70h). In SMBus mode, the DS28CM00 resets its communication interface if it detects a bus fault condition. FEATURES Unique, Factory-Lasered and Tested 64-bit Registration Number (8-bit Family Code + 48-bit Serial Number + 8-bit CRC) SMBus-Compatible IC Serial Interface Supports 100kHz and 400kHz Communication Speeds 5V Tolerant Interface Pins Operating Range: 1.8V 10% to 5V 5%, -40C to +85C 5-Pin SOT23 Package APPLICATIONS Printed Circuit Board Unique Serialization Accessory and Peripheral Identification Equipment Registration and License Management Network Node Identification ORDERING INFORMATION PART DS28CM00R-A00+T TEMP RANGE -40C to +85C PIN-PACKAGE SOT23-5 Tape-and-Reel +Denotes lead-free package. TYPICAL OPERATING CIRCUIT VCC RP VCC SDA SCL RP PIN CONFIGURATION SCL GND SDA 1 2 3 4 NC 5 VCC C GND VCC SDA SCL DS28CM00 GND SOT23 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 9 REV: 072406 DS28CM00: IC/SMBus Silicon Serial Number ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Maximum Current Into Any Pin Operating Temperature Range Junction Temperature Storage Temperature Range Soldering Temperature -0.5V, +6V 20mA -40C to +85C +150C -55C to +125C See IPC/JEDEC J-STD-020 Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device. ELECTRICAL CHARACTERISTICS (-40C to +85C, see Note 1) PARAMETER Supply Voltage Standby Current Operating Current SYMBOL VCC ICCS ICCA CONDITIONS Bus idle, VCC = 5.25V Bus active at 400kHz, VCC = 5.25V VCC 2.0V LOW Level Input Voltage VIL VCC < 2.0V HIGH Level Input Voltage (Note 3) VCC 2.0V VIH VCC < 2.0V VCC 2.0V Vhys VCC < 2.0V VOL VCC 2.0V tof VCC < 2.0V tSP Ii Ci fSCL tTIMEOUT tHD:STA SDA and SCL pins only (Note 4) (Note 6) (Note 4) VCC 2.0V VCC < 2.0V (Note 7) (Note 8) VCC 2.7V VCC 2.0V VCC < 2.0V (Note 8) (Note 8) 2 of 9 -10 20 + 0.1Cb 20 + 0.1Cb -0.3 0.7 x VCC 0.8 x VCC 0.05 x VCC 0.1 x VCC MIN 1.62 TYP MAX 5.25 3 200 UNITS V A A SCL, SDA Pins (Note 2) See Figure 5 -0.3 0.3 x VCC 0.25 x VCC VCCmax + 0.3V VCCmax + 0.3V V V Hysteresis of Schmitt Trigger Inputs (Note 4) LOW Level Output Voltage at 4mA Sink Current Output Fall Time from VIhmin to VILmax with a Bus Capacitance from 10pF to 400pF (Notes 4, 5) Pulse Width of Spikes that are Suppressed by the Input Filter Input Current with an Input Voltage Between 0.1VCC and 0.9VCCmax Input Capacitance SCL Clock Frequency (Note 7) Bus Time-out Hold Time (Repeated) START Condition. After this Period, the First Clock Pulse is Generated. LOW Period of the SCL Clock (Note 8) HIGH Period of the SCL Clock Setup Time for a Repeated START Condition V 0.4 250 V ns 450 50 10 10 400 344 75 ns A pF kHz ms s 25 0.6 1.3 1.5 2.3 0.6 0.6 tLOW tHIGH tSU:STA s s s DS28CM00: IC/SMBus Silicon Serial Number PARAMETER Data Hold Time (Notes 9, 10) Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Capacitive Load for Each Bus Line SYMBOL tHD:DAT tSU:DAT tSU:STO tBUF Cb CONDITIONS VCC 2.7V VCC 2.0V VCC < 2.0V (Notes 8, 11) (Note 8) (Note 8) (Notes 4, 8) MIN 0.3 0.3 0.3 100 0.6 1.3 400 TYP MAX 0.9 1.1 1.7 UNITS s ns s s pF Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Specifications at -40C are guaranteed by design and characterization only and not production tested. All values are referred to VIHmin and VILmax levels. The maximum specification value is guaranteed by design, not production tested. Not production tested. Guaranteed by design or characterization. CB = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according to I2C-Bus Specification v2.1 are allowed. The DS28CM00 does not obstruct the SDA and SCL lines if VCC is switched off. The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 AND SCL stays at the same logic level or SDA stays low for this interval, the DS28CM00 behaves as though it has sensed a STOP condition. System Requirement The DS28CM00 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal. A Fast-mode IC-bus device can be used in a standard-mode IC-bus system, but the requirement tSU:DAT 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU:DAT = 1000 + 250 = 1250ns (according to the standard-mode IC-bus specification) before the SCL line is released. PIN DESCRIPTION PIN 1 2 3 4 5 NAME SCL GND SDA N.C. VCC FUNCTION Serial interface clock input; must be tied to VCC through a pullup resistor. 5V tolerant input over 1.62V to 5.25V VCC range. Ground supply for the device. Serial interface bi-directional data line; must be tied to VCC through a pullup resistor. 5V tolerant input/output over 1.62V to 5.25V VCC range. Not Connected Power Supply Input OVERVIEW The DS28CM00 consists of a serial interface which provides access to a unique 64-bit Registration number and a Control Register, as shown in the block diagram in Figure 1. The device communicates with a host processor through its SMBus compatible IC bus interface in standard-mode or in fast-mode. Since the network address of the DS28CM00 is fixed, exactly one device can reside on a bus segment. The Registration Number and Control Register are located in a linear 9-byte address space (Figure 2). 3 of 9 DS28CM00: IC/SMBus Silicon Serial Number Figure 1. Block Diagram VCC SCL SDA Serial Interface ROM Registration Number Control Register GND Figure 2. Memory Map ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h TYPE ROM ROM ROM ROM ROM ROM ROM ROM SRAM ACCESS Read Read Read Read Read Read Read Read R/W DESCRIPTION Device Family Code (70h) Serial Number, bits 0 to 7 Serial Number, bits 8 to 15 Serial Number, bits 16 to 23 Serial Number, bits 24 to 31 Serial Number, bits 32 to 39 Serial Number, bits 40 to 47 CRC of Family Code and 48-bit Serial Number Control Register Unique Registration Number Each DS28CM00 has a unique Registration Number that is 64 bits long. The registration number begins with the family code at address 00h followed by the 48-bit serial number (LS-byte at the lower address) and ends at address 07h with the CRC (Cyclic Redundancy Check) of the first 56 bits. This CRC is generated using the polynomial X8 + X5 + X4 + 1. Additional information about CRCs is available in Application Note 27. The ROM Registration Number is not related to the IC slave address of the device. Control Register The Control Register at address 08h allows switching between IC mode and SMBus mode. Only the LS bit of this register, referred to as the CM bit, has a function. The other 7 bits always read 0 and cannot be changed. When the CM bit is set to 1 (power-on default), the device is in SMBus mode, which enables the bus timeout function. Setting the CM bit to 0 puts the device in IC mode, where the timeout function is disabled. In SMBus mode, the serial interface times out and is internally reset if SCL is stuck (high or low) or if SDA is stuck low for the duration of tTIMEOUT or longer. This reset turns the SDA line into an input, ensuring that the device is ready to recognize a communication start condition. ADDR 08h b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 CM 4 of 9 DS28CM00: IC/SMBus Silicon Serial Number DEVICE OPERATION Typically, the DS28CM00 is accessed after power-up to read the 64-bit Registration number, which may serve to identify the object that the device is embedded in. Write access exists only to the Control Register. Read and write access are controlled through the IC/SMBus serial interface. See section Read and Write for details. Serial Communication Interface General Characteristics The serial interface uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no communication, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data can be transferred at rates of up to 100kbps in the Standard-mode, up to 400kbps in the Fast-mode. The DS28CM00 works in both modes. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the communication is called a "master." The devices that are controlled by the master are "slaves." The DS28CM00 is a slave device. Slave Address/Direction Byte To be individually accessed, each device must have a slave address that does not conflict with other devices on the bus. The slave address to which the DS28CM00 responds is shown in Figure 3. The slave address is part of the slave-address/direction byte. The last bit of the slave-address/direction byte (R/W) defines the data direction. When set to a 0, subsequent data will flow from master to slave (write access mode); when set to a 1, data will flow from slave to master (read access mode). Figure 3. DS28CM00 Slave Address 7-Bit Slave Address A6 1 A5 0 A4 1 A3 0 A2 0 A1 0 A0 0 R/W Most Significant Bit Determines Read or Write IC/SMBus Protocol Data transfers may be initiated only when the bus is not busy. The master generates the serial clock (SCL), controls the bus access, generates the START and STOP conditions, and determines the number of bytes transferred between START and STOP (Figure 4). Data is transferred in bytes with the most significant bit being transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave. During any data transfer, SDA must remain stable whenever the clock line is HIGH. Changes in SDA line while SCL is high will be interpreted as a START or a STOP. The protocol is illustrated in Figure 4. For detailed timing references see Figure 5. 5 of 9 DS28CM00: IC/SMBus Silicon Serial Number Figure 4. IC/SMBus Protocol Overview MS-bit SDA Slave Address Acknowledgment from Receiver Repeated if more bytes are transferred R/W ACK bit ACK bit SCL Idle START Condition 1 2 6 7 8 9 ACK 1 2 8 9 ACK STOP Condition Repeated START Condition Bus Idle or Not Busy Both, SDA and SCL, are inactive, i. e., in their logic HIGH states. START Condition To initiate communication with a slave, the master has to generate a START condition. A START condition is defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH. STOP Condition To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as a change in state of SDA from LOW to HIGH while SCL remains HIGH. Repeated START Condition Repeated starts are commonly used for read accesses to select a specific data source or address to read from. The master can use a repeated START condition at the end of a data transfer to immediately initiate a new data transfer following the current one. A repeated START condition is generated the same way as a normal START condition, but without leaving the bus idle after a STOP condition. Data Valid With the exception of the START and STOP condition, transitions of SDA may occur only during the LOW state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL, see Figure 5). There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL pulse. When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum tSU:DAT + tR in Figure 5) before the next rising edge of SCL to start reading. The slave shifts out each data bit on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. The master generates all SCL clock pulses, including those needed to read from a slave. Acknowledged Usually, a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte. The master must generate a clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW during the HIGH period of the acknowledge-related clock pulse plus the required setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL). 6 of 9 DS28CM00: IC/SMBus Silicon Serial Number Not Acknowledged by Slave A slave device may be unable to receive or transmit data, e.g., because it is busy. As a SMBus-compatible device, the DS28CM00 will always acknowledge its slave address. However, some time later the slave may refuse to accept data, e.g., because of an invalid memory address or access mode, e. g. attempting to write to a ROM byte. In this case the slave device will not acknowledge any of the bytes that it refuses and will leave SDA HIGH. After a slave has failed to acknowledge, the master should generate a repeated START condition or a STOP condition followed by a START condition to begin a new data transfer. Not Acknowledged by Master At some time when receiving data, the master must signal an end of data to the slave device. To achieve this, the master does not acknowledge the last byte that it has received from the slave. In response, the slave releases SDA, allowing the master to generate the STOP condition. Figure 5. IC/SMBus Timing Diagram SDA tBUF tLOW tF tHD:STA tSP SCL tHD:STA tR tHD:DAT STOP START tHIGH tSU:DAT Repeated START tSU:STA Spike Suppression tSU:STO NOTE: Timing is referenced to VILMAX and VIHMIN. Read and Write The DS28CM00 behaves like an IC memory device with an 9-byte memory map (Figure 2). The memory consists of 8 bytes ROM and one byte SRAM, i. e., the Control Register. The ROM data cannot be changed. To write to the DS28CM00, the master must access the device in write access mode, i.e., the slave address must be sent with the direction bit set to 0. The next byte to be sent in write access mode is an address byte to set the address pointer to a specific location. The DS28CM00 acknowledges any address between 00h and 08h. Write attempts to the ROM are ignored and data received for these addresses is not acknowledged. However, the address pointer increments after every full data byte transmitted by the master and rolls over from 08h to 00h after a full data byte is written to address 08h. To read from the DS28CM00, the master must access the device in read access mode, i.e., the slave address must be sent with the direction bit set to 1. The address pointer determines the location from which the master will start reading. The pointer is set when the DS28CM00 is accessed in write access mode, as described above. The power-on default of the pointer is 00h. When reading from the device, the address pointer increments with every data byte read. When the end of the memory is reached (address 08h), the address pointer wraps around to 00h. To read from an arbitrary address, the master must first access the DS28CM00 in write access mode and specify a new memory address. The address pointer remains unchanged if the device resets its communication interface due to a bus timeout in SMBus mode. 7 of 9 DS28CM00: IC/SMBus Silicon Serial Number IC CommunicationLegend SYMBOL S AD,0 AD,1 Sr P DESCRIPTION START Condition Select DS28CM00 for Write Access Select DS28CM00 for Read Access Repeated START Condition STOP Condition SYMBOL A A\ Command-Specific CommunicationColor-Codes Master-to-Slave Slave-to-Master Communication Examples Write to Control Register (address 08) S AD,0 A 08h A Write to ROM Address (excludes address 08) S AD,0 A VMA A Set address pointer Application Information SDA and SCL Pullup Resistors SDA is an open-drain output on the DS28CM00 that requires a pullup resistor (Figure 6) to realize high logic levels. Because the DS28CM00 uses SCL only as input (no clock stretching) the master can drive SCL either through an open-drain/collector output with a pullup resistor or a push-pull output. Pullup Resistor RP Sizing According to the IC specification, a slave device must be able to sink at least 3mA at a VOL of 0.4V. The SMBus specification requires a current sink capability of 4mA at 0.4V. The DS28CM00 can sink at least 4mA at 0.4V VOL over its entire operating voltage range. This DC characteristic determines the minimum value of the pullup resistor: Rpmin = (VCC - 0.4V)/4mA. With a maximum operating voltage of 5.25V, the minimum value for the pullup resistor is 1.2k. The "Minimum RP" line in Figure 7 shows how the minimum pullup resistor changes with the operating (pullup) voltage. 8 of 9 DS28CM00: IC/SMBus Silicon Serial Number Figure 6. Application Schematic VCC RP VCC SDA SCL To additional devices VCC SDA SCL DS28CM00 GND RP C GND For IC systems, the rise time and fall time are measured from 30% to 70% of the pullup voltage. The maximum bus capacitance CB is 400pF. The maximum rise time must not exceed 300ns. Assuming maximum rise time, the maximum resistor value at any given capacitance CB is calculated as: RPMAX = 300ns/(CB*ln(7/3)). For a bus capacitance of 400pF the maximum pullup resistor would be 885. Since a 885 pullup resistor, as would be required to meet the rise time specification and 400pF bus capacitance, is lower than RPMIN at 5.25V, a different approach is necessary. The "Max. Load..." line in Figure 7 is generated by first calculating the minimum pullup resistor at any given operating voltage ("Minimum RP" line) and then calculating the respective bus capacitance that yields a rise time of 300ns. Only for pullup voltages of 4V and lower can the maximum permissible bus capacitance of 400pF be maintained. A reduced bus capacitance of 300pF is acceptable for the entire operating voltage range. The corresponding pullup resistor value at the voltage is indicated by the "Minimum RP" line. Figure 7. IC Fast Speed Pullup Resistor Selection Chart "Minimum Rp" 1200 Minimum Rp (Ohms) 1000 800 600 400 200 0 1.5 2 2.5 3 3.5 4 4.5 5 Pull-up Voltage Max. Load at Min. Rp fast mode 600 500 Load (pF) 400 300 200 100 0 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) 9 of 9 |
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